1. Field of the Invention
The present invention relates to processor instruction sets, and more particularly to fixed length instruction sets for processors.
2. Description of Background Art
Over the past few years, Internet connectivity has been increasing at an astounding rate. Embedded processors are being increasingly used to provide this connectivity. Internet processing has little arithmetic, but involves manipulation of memory buffers for packets and headers. A lot of data is moved without being transformed, especially in the communications field. Another often encountered task is to change or examine bit-fields in headers.
Conventionally, Reduced Instruction Set Computer (RISC) or Complex Instruction Set Computer (CISC) processors have been used for these tasks. However, both RISC and CISC prove to be problematic, especially when dealing with narrow data (e.g., 16-bit data) which is common in the communications field.
When data in memory needs to be manipulated, RISC processors traditionally move data from memory to registers (“Load”), perform the desired arithmetic calculations on them, and then move the result back from the register to memory (“Store”). The Arithmetic Logic Unit (ALU) instructions and the data from the registers are 32-bit wide in RISC processors. The data from memory may be of 8, 16, or 32 bits. If the data is 8 or 16 bits wide, it is sign extended to make it 32 bits before arithmetic is performed on it. Once the arithmetic is performed, it is truncated to 8 or 16 bits and then stored in memory. Due to the Load & Store architecture of RISC processors, numerous instructions are often required for simple operations. In addition, one RISC instruction can use at most one memory operand (e.g., load and store instructions), or no memory operands (e.g., arithmetic instructions).
In CISC processors, operations can be performed on data in memory without having to load and then later store the data. The instruction set itself specifies the width of the operands, as well as the width of the arithmetic. However, in order to do this, the instruction set in CISC processors is variable in length.
Further, although many conventional chips include Direct Memory Access (DMA) engines to offload data movement from the main processor and special purpose assists, these DMA engines or special purpose assists take up valuable silicon real-estate, and make the software more complex.
In the communications field, narrow data (e.g., 16-bit data or 8-bit data) needs to be dealt with efficiently. In particular, communications data is often 16 bits wide. Therefore similar support for 32-bit wide data and 16-bit wide data is needed. That is, a processor should be similarly robust for processing 32-bit wide data as well as 16-bit data. At the same time, keeping the arithmetic and register data at 32 bits simplifies the hardware design. However, narrow data in 32-bit registers can be problematic. One of the reasons why 16-bit data in 32 bit registers complicates hardware is because it can result in partial register writes. A partial register write occurs as a result of an instruction which changes part of a register and leaves the rest of the register unmodified. In a pipelined machine, the bypassing of data from one instruction to the next becomes much more complicated because of partial writes. Further, instructions may need to be specific regarding which part of a 32-bit register to use.
In conventional systems, memory operand width is dependent on ALU width. For instance, if the ALU is 32 bits wide, the memory operand is also 32 bits wide. In contrast, if the memory operand width were to be independent of the ALU width, data could be stored more efficiently in memory. For instance, if the memory operand were to be, say, 16 bits wide, it could be stored in memory as 16-bit data, rather than extending it to 32 bits.
Therefore, what is needed is (1) a processor with memory operand widths which are independent of the ALU width; (2) a processor to provide similarly robust processing for 32-bit and 16-bit data, without significantly increasing the complexity of hardware and software; and (3) fixed-length instructions which can have multiple memory operands.